In the role of FPGA Developer, you will play a critical role in deploying our electronics in multiple space applications. As a key member of a highly professional and supportive team, you will collaborate with our hardware and software experts to design, develop, and test FPGA logic implementations. By supporting both delivery of our standard products and for custom design projects, your FPGA logic will play critical roles in missions on Low Earth Orbit, in lunar applications, and beyond.

Specifically, you will execute the following functions:

Generate logic projects to support our embedded Q-card platforms:

Xilinx Vivado: Zynq, UltraScale+ and Versal
Microsemi Libero: ProASIC3 and PolarFire
Write physical and timing constraints, meet timings
Propose and implement pinouts for new designs

FPGA logic design

Custom IP cores creation
Define requirements, interfaces, ports, and parameters
VHDL - Verilog coding
Verification and simulation
Vendor and third-party IP core integration
High-Speed examples: PCIe, Gig Ethernet, JESD
Low-Speed examples: UART, SPI, I2C
Documentation
Logic architecture, description, interfaces, clock and reset scheme, register map

Automated Verification (simulation)

Testbench creation, write self check unit tests, regression testing
Firmware release support

FPGA IP Core library maintenance
FPGA Infrastructure

Contribute to put in place a build farm
Automate register interfaces
Scripting : Project creation, automated pinouts, FPGA bistream generation

Participate to the logic design and review process
Support to the test team and customers' de-bugging

DESIREABLE KNOWLEDGE AREAS

Coding languages

VHDL,
Verilog and System Verilog are good assets

Advanced Verification is an asset (OSSVM, UVM)
FPGA Physical design and optimisation
Timing closure
FPGA Development

Xilinx Vivado
Microsemi Libero an asset
Vivado HLS an asset

Simulation Tool (one among the list)

Modelsim, Questa
Active-HDL, Rivera Pro
Vivado Simulator

Good understanding of synchronous design

Clocking, pipeline, clock domain crossing
Clock enable, reset, back pressure
FIFO
PLL
DSP knowledge is an asset

Scripting Languages

Python, TCL is an asset, Bash is an asset

Revision Control

FPGA Interconnect Interfaces like AMBA AXI, AHB
Debugging in the lab

PERSONAL ATTRIBUTES

Autonomous
Show initiative
Rigorous and methodological approaches
Engaged
Capacity to take responsibility
Good analysis skills

QUALIFICATIONS

Completed Bachelor's or Master's degree in Engineering, Computer Science, or other related area of study
A minimum of 10 years of experience working with FPGAs
Must be able to obtain Canadian government security clearance
Bilingual

Xiphos

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