As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all.
As a DFT Engineer you will work with chip architects, chip designers, implementation engineers and test engineers to verify the DFT and DFD (Design for Debug) architecture, implementation, and test plans for both mixed signal and digital VLSI designs. Then you’ll insure it becomes reality. We’re doing a ground up implementation of a new chip architecture, so you’ll have to ability to affect a new design.
Qualifications:
BA/BS degree in Electrical/Computer Engineering with 3+ years of practical experience
Strong fundamentals in digital ASIC design; experience using Verilog or VHDL
Experience with ASIC test, DFT, and debug
10+ years of practical experience with test or DFT
Experience using the Mentor Tessent tools
Experience with defining and implementing SOC level verification on large designs.
Experience in TCL, Perl/Python and Shell scripting
Preferred Qualifications:
Hands-on expertise with commercial test generation tools for large complex designs
Strong fundamental knowledge of DFT techniques include JTAG, ATPG, test pattern translation, yield learning, logic diagnosis, scan compression, IEEE 1500 Standard, and MBIST, LBIST
Experience running test compression software
Strong sense of ownership, self-driven
Roles and Responsibilities:
Create test vectors or oversee their creation
Validate DFT requirements are being met
Work with designers to increase test coverage, debug observability and flexibility
Verify post-PD designs meet DFT requirements
Work with test personnel, stepping in to do run tests when needed
