Are you a creative engineer looking for challenges to develop technologies that improve people’s everyday life? The Qualcomm Low Power Machine Learning IP team is looking for a strong ASIC design verification engineer for an exciting opportunity to join our effort in developing world class ML HW solutions.
As a member of the team, your responsibilities include:
Work closely with design, architects, and verification leads to develop the IP verification strategy and testplan
Create verification environment using UVM/System verilog
Resolve architecture, design, or verification problems by applying sound ASIC engineering practices
Write tests and regressions to identify any bugs in own work and helps more junior team members do the same
Interpret the results of performance checks and identify issues
Communicate directly with lead on any significant deviations from the Plan of Record for assigned block in a timely manner
Perform RTL code coverage, assertion coverage, functional coverage, and gate level simulations
Identify opportunity for productivity improvements. Drive and adopt new verification methodologies and flows for efficiency improvements
Effectively utilize advanced problem solving and ASIC engineering practices to resolve complex problems
Required Competencies:
Ability to work legally in Canada
Thorough understanding of Digital design concepts
Strong UVM, System Verilog skills
Understanding of Bus protocols like AHB/AXI
Perl, python scripting experience
Quick understanding of Specs and Standards and developing relevant and thorough test plans
Experienced in developing monitors, scoreboards, sequencers and sequences and various aspects of the UVM test benches
Candidates should be comfortable checking builds, navigating test benches, analyzing coverage, and adding or enabling extra debug
Strong communication skills and works well in a team environment
