The responsibilities of this role include:
• Working with DPU architecture teams to define, document and implement DPU models
• Integrate display IP Cmodels to the display ASIC verification environment
• Collaborate with SoC architects, display hardware and software teams to evaluate new features and understand design tradeoffs.
• Analyze simulation results to identify bottlenecks and opportunities for improvements.
• Present analysis results and provide recommendations.
• Provides software configuration libraries
Minimum Qualification:
• C/C++ programming
• Strong scripting for automation using Perl, Python
• Software development
• Critical thinking, analytical and organizational skills are mandatory.
• Strong presentation and communication skills.
Preferred Qualifications:
• ASIC design and verification: VHDL, Verilog, System Verilog
• Experience of c-modeling tools, including C/C++, SystemC, Excel
• Experience debugging complex system C models.
• Strong technical background in display
Educational Requirements:
In study towards a bachelor’s degree in one of the following: Electrical Engineering, Computer Engineering, Engineering Science, Computer Science, or related field
Eligible candidates must have a graduation date in December 2027 or later, including May or June 2028.
For 16-month internships: must be available May 2026 - August 2027
